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Renesas Electronics /R7FA6M3AH /GLCDC /OUT_CONTRAST

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Interpret as OUT_CONTRAST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CONTR)CONTR0 (CONTB)CONTB0 (CONTG)CONTG

CONTR=CONTR, CONTB=CONTB, CONTG=CONTG

Description

Output Control Block Contrast Correction Register

Fields

CONTR

Contrast (GAIN) adjustment of R signalUnsigned; 8 bits fixed point

0 (CONTR): CONTR/128
CONTB

Contrast (GAIN) adjustment of B signalUnsigned; 8 bits fixed point

0 (CONTB): CONTB/128
CONTG

Contrast (GAIN) adjustment of G signalUnsigned; 8 bits fixed point.

0 (CONTG): CONTG/128

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data